This glossary describes some of the terms used in technical documents from ARM Limited.
A mechanism that indicates to a core that the attempted memory access is invalid or not allowed or that the data returned by the memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid or protected instruction or data memory.
See Also Data Abort, External Abort and Prefetch Abort.
- Addressing modes
Various mechanisms, shared by many different instructions, for generating values used by the instructions.
- Advanced High-performance Bus (AHB)
A bus protocol with a fixed pipeline between address/control and data phases. It only supports a subset of the functionality provided by the AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave IP developments and ARM Limited recommends only a subset of the protocol is usually used. This subset is defined as the AMBA AHB-Lite protocol.
See Also Advanced Microcontroller Bus Architecture and AHB-Lite.
- Advanced Microcontroller Bus Architecture (AMBA)
A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC). It aids in the development of embedded processors with one or more CPUs or signal processors and multiple peripherals. AMBA complements a reusable design methodology by defining a common backbone for SoC modules.
- Advanced Peripheral Bus (APB)
A simpler bus protocol than AXI and AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption.
See Advanced High-performance Bus.
- AHB Access Port (AHB-AP)
An optional component of the DAP that provides an AHB interface to a SoC.
See AHB Access Port.
A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by the majority of AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect. In most cases, the extra facilities provided by a full AMBA AHB interface are implemented more efficiently by using an AMBA AXI protocol interface.
- AHB Trace Macrocell
A hardware macrocell that, when connected to a processor core, outputs data trace information on a trace port.
A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively.
See Advanced Microcontroller Bus Architecture.
- Advanced Trace Bus (ATB)
A bus used by trace devices to share CoreSight capture resources.
See Advanced Peripheral Bus.
- Application Specific Integrated Circuit (ASIC)
An integrated circuit that has been designed to perform a specific application function. It can be custom-built or mass-produced.
- Application Specific Standard Part/Product (ASSP)
An integrated circuit that has been designed to perform a specific application function. Usually consists of two or more separate circuit functions combined as a building block suitable for use in a range of products for one or more specific application markets.
The organization of hardware and/or software that characterizes a processor and its attached components, and enables devices with similar characteristics to be grouped together when describing their behavior, for example, Harvard architecture, instruction set architecture, ARMv7-M architecture.
- ARM instruction
An instruction of the ARM Instruction Set Architecture (ISA). These cannot be executed by the Cortex-M3.
- ARM state
The processor state in which the processor executes the instructions of the ARM ISA. The processor only operates in Thumb state, never in ARM state.
See Application Specific Integrated Circuit.
See Application Specific Standard Part/Product.
See Advanced Trace Bus.
- ATB bridge
A synchronous ATB bridge provides a register slice to facilitate timing closure through the addition of a pipeline stage. It also provides a unidirectional link between two synchronous ATB domains.
An asynchronous ATB bridge provides a unidirectional link between two ATB domains with asynchronous clocks. It is intended to support connection of components with ATB ports residing in different clock domains.
- Base register
A register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory.
- Base register write-back
Updating the contents of the base register used in an instruction target address calculation so that the modified address is changed to the next higher or lower sequential address in memory. This means that it is not necessary to fetch the target address for successive instruction transfers and enables faster burst accesses to sequential memory.
Alternative word for an individual data transfer within a burst. For example, an INCR4 burst comprises four beats.
Big-endian view of memory in a byte-invariant system.
See Also BE-32, LE, Byte-invariant and Word-invariant.
Big-endian view of memory in a word-invariant system.
See Also BE-8, LE, Byte-invariant and Word-invariant.
Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory.
See Also Little-endian and Endianness.
- Big-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address
a byte at a halfword-aligned address is the most significant byte within the halfword at that address.
See Also Little-endian memory.
- Boundary scan chain
A boundary scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO, through which test data is shifted. Processors can contain several shift registers to enable you to access selected parts of the device.
- Branch folding
Branch folding is a technique where the branch instruction is completely removed from the instruction stream presented to the execution pipeline.
A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested.
See Also Watchpoint.
A group of transfers to consecutive addresses. Because the addresses are consecutive, there is no requirement to supply an address for any of the transfers after the first one. This increases the speed at which the group of transfers can occur. Bursts over AMBA are controlled using signals to indicate the length of the burst and how the addresses are incremented.
See Also Beat.
An 8-bit data item.
In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported. Multi-word accesses are expected to be word-aligned.
See Also Word-invariant.
- Clock gating
Gating a clock signal for a macrocell with a control signal and using the modified clock that results to control the operating state of the macrocell.
- Clocks Per Instruction (CPI)
See Cycles Per Instruction (CPI).
- Cold reset
Also known as power-on reset.
See Also Warm reset.
The environment that each process operates in for a multitasking operating system.
See Also Fast context switch.
A core is that part of a processor that contains the ALU, the datapath, the general-purpose registers, the Program Counter, and the instruction decode and control circuitry.
- Core reset
See Warm reset.
The infrastructure for monitoring, tracing, and debugging a complete system on chip.
See Cycles per instruction.
- Cycles Per instruction (CPI)
Cycles per instruction (or clocks per instruction) is a measure of the number of computer instructions that can be performed in one clock cycle. This figure of merit can be used to compare the performance of different CPUs that implement the same instruction set against each other. The lower the value, the better the performance.
- Data Abort
An indication from a memory system to the core of an attempt to access an illegal data memory location. An exception must be taken if the processor attempts to use the data that caused the abort.
See Also Abort.
- DCode Memory
Memory space at
- Debug Access Port (DAP)
A TAP block that acts as an AMBA, AHB or AHB-Lite, master for access to a system bus. The DAP is the term used to encompass a set of modular blocks that support system wide debug. The DAP is a modular component, intended to be extendable to support optional access to multiple systems such as memory mapped AHB and CoreSight APB through a single debug interface.
A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.
- Embedded Trace Macrocell (ETM)
A hardware macrocell that, when connected to a processor core, outputs instruction trace information on a trace port.
Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping.
See Also Little-endian and Big-endian.
See Embedded Trace Macrocell.
An error or event which can cause the processor to suspend the currently executing instruction stream and execute a specific exception handler or interrupt service routine. The exception could be an external interrupt or NMI, or it could be a fault or error event that is considered serious enough to require that program execution is interrupted. Examples include attempting to perform an invalid memory access, external interrupts, and undefined instructions. When an exception occurs, normal program flow is interrupted and execution is resumed at the corresponding exception vector. This contains the first instruction of the interrupt service routine to deal with the exception.
- Exception handler
See Interrupt service routine.
- Exception vector
See Interrupt vector.
- External PPB
PPB memory space at
- Flash Patch and Breakpoint unit (FPB)
A set of address matching tags, that reroute accesses into flash to a special part of SRAM. This permits patching flash locations for breakpointing and quick fixes or changes.
The formatter is an internal input block in the ETB and TPIU that embeds the trace source ID within the data to create a single trace stream.
A 16-bit data item.
- Halt mode
One of two mutually exclusive debug modes. In halt mode all processor execution halts when a breakpoint or watchpoint is encountered. All processor state, coprocessor state, memory and input/output locations can be examined and altered by the JTAG interface.
See Also Monitor debug-mode.
A computer that provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.
See AHB Trace Macrocell.
- ICode Memory
Memory space at
- Illegal instruction
An instruction that is architecturally Undefined.
The behavior is not architecturally defined, but is defined and documented by individual implementations.
The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility.
- Instruction cycle count
The number of cycles for which an instruction occupies the Execute stage of the pipeline.
- Instrumentation trace
A component for debugging real-time systems through a simple memory-mapped trace interface, providing
- Intelligent Energy Management (IEM)
A technology that enables dynamic voltage scaling and clock frequency variation to be used to reduce power consumption in a device.
- Internal PPB
PPB memory space at
- Interrupt service routine
A program that control of the processor is passed to when an interrupt occurs.
- Interrupt vector
One of a number of fixed addresses in low memory that contains the first instruction of the corresponding interrupt service routine.
- Joint Test Action Group (JTAG)
The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.
See Joint Test Action Group.
- JTAG Debug Port (JTAG-DP)
An optional external interface for the DAP that provides a standard JTAG interface for debug access.
See JTAG Debug Port.
Little endian view of memory in both byte-invariant and word-invariant systems. See also Byte-invariant, Word-invariant.
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory.
See Also Big-endian and Endianness.
- Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See Also Big-endian memory.
- Load/store architecture
A processor architecture where data-processing operations only operate on register contents, not directly on memory contents.
- Load Store Unit (LSU)
The part of a processor that handles load and store transfers.
See Load Store Unit.
A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells (such as a processor, an ETM, and a memory block) plus application-specific logic.
- Memory coherency
A memory is coherent if the value read by a data read or instruction fetch is the value that was most recently written to that location. Memory coherency is made difficult when there are multiple possible physical locations that are involved, such as a system that has main memory, a write buffer and a cache.
- Memory Protection Unit (MPU)
Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does not modify addresses.
- Monitor debug-mode
One of two mutually exclusive debug modes. In Monitor debug-mode the processor enables a software abort handler provided by the debug monitor or operating system debug task. When a breakpoint or watchpoint is encountered, this enables vital system interrupts to continue to be serviced while normal program execution is suspended.
See Also Halt mode.
See Memory Protection Unit.
An interconnect scheme similar to a cross-bar switch. Each master on the interconnect has a direct link to each slave, The link is not shared with other masters. This enables each master to process transfers in parallel with other masters. Contention only occurs in a multi-layer interconnect at a payload destination, typically the slave.
The number of cycles in which no useful Execute stage pipeline activity can occur because an instruction flow is different from that assumed or predicted.
See Prefetch Unit.
- Power-on reset
See Cold reset.
See Private Peripheral Bus.
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed.
- Prefetch Abort
An indication from a memory system to the core that an instruction has been fetched from an illegal memory location. An exception must be taken if the processor attempts to execute the instruction. A Prefetch Abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory.
See Also Data Abort, Abort.
- Prefetch Unit (PFU)
The PFU fetches instructions from the memory system that can supply one word each cycle. The PFU buffers up to three word fetches in its FIFO, which means that it can buffer up to three Thumb-2 instructions or six Thumb instructions.
- Private Peripheral Bus
Memory space at
A processor is the circuitry in a computer system required to process data using the computer instructions. It is an abbreviation of microprocessor. A clock source, power supplies, and main memory are also required to create a minimum complete working computer system.
- RealView ICE
A system for debugging embedded processor cores using a JTAG interface.
A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation‑specific. All reserved bits not used by the implementation must be written as 0 and read as 0.
See Should Be One.
See Should Be Zero.
See Should Be Zero or Preserved.
- Scan chain
A scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO, through which test data is shifted. Processors can contain several shift registers to enable you to access selected parts of the device.
- Should Be One (SBO)
Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 produces Unpredictable results.
- Should Be Zero (SBZ)
Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 produces Unpredictable results.
- Should Be Zero or Preserved (SBZP)
Should be written as 0 (or all 0s for bit fields) by software, or preserved by writing the same value back that has been previously read from the same field on the same processor.
- Serial-Wire Debug Port
An optional external interface for the DAP that provides a serial-wire bidirectional debug interface.
- Serial-Wire JTAG Debug Port
A standard debug port that combines JTAG-DP and SW-DP.
See Serial-Wire Debug Port.
See Serial-Wire JTAG Debug Port.
- Synchronization primitive
The memory synchronization primitive instructions are those instructions that are used to ensure memory synchronization. That is, the LDREX and STREX instructions.
- System memory
Memory space at
0xFFFFFFFF, excluding PPB space at
See Test access port.
- Test Access Port (TAP)
The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic.
- Thread Control Block
A data structure used by an operating system kernel to maintain information specific to a single thread of execution.
- Thumb instruction
A halfword that specifies an operation for an ARM processor in Thumb state to perform. Thumb instructions must be halfword-aligned.
- Thumb state
A processor that is executing Thumb (16-bit) halfword aligned instructions is operating in Thumb state.
See Trace Port Analyzer.
See Trace Port Interface Unit.
- Trace Port Interface Unit (TPIU)
Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a TPA.
A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four.
For reads, the data returned when reading from this location is unpredictable. It can have any value. For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration. Unpredictable instructions must not halt or hang the processor, or any part of the system.
- Warm reset
Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor.
A watchpoint is a mechanism provided by debuggers to halt program execution when the data contained by a particular memory address is changed. Watchpoints are inserted by the programmer to enable inspection of register contents, memory locations, and variable values when memory is written to test that the program is operating correctly. Watchpoints are removed after the program is successfully tested. See also Breakpoint.
A 32-bit data item.
In a word-invariant system, the address of each byte of memory changes when switching between little-endian and big-endian operation, in such a way that the byte with address A in one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of memory always consists of the same four bytes of memory in the same order, regardless of endianness. The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged.The ARM architecture supports word-invariant systems in ARMv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions that are given unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access. It is recommended that word-invariant systems use the endianness that produces the required byte addresses at all times, apart possibly from very early in their reset handlers before they have set up the endianness, and that this early part of the reset handler must use only aligned word memory accesses.
See Also Byte-invariant.
- Write buffer
A pipeline stage for buffering write data to prevent bus stalls from stalling the processor.