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9.3. MPU access permissions

This section describes the MPU access permissions. The access permission bits, TEX, C, B, AP, and XN, of the Region Access Control Register (see MPU Region Attribute and Size Register) control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then a permission fault is raised.

Table 9.8 describes the TEX, C, and B encoding.

TEX, C, B encoding
TEXCBDescriptionMemory typeRegion shareability
b0000 0 Strongly ordered.Strongly orderedShareable
b0000 1 Shared device.DeviceShareable
b0001 0 Outer and inner write-through. No write allocate.NormalS
b0001 1 Outer and inner write-back. No write allocate.NormalS
b0010 0 Outer and inner noncacheable.NormalS
b0010 1 Reserved.ReservedReserved
b0011 0 Implementation-defined.
b0011 1 Outer and inner write-back. Write and read allocate.NormalS
b01000 Nonshared device.DeviceNot shareable
b01001 Reserved.ReservedReserved

Cached memory BB = outer policy.

AA = inner policy.



In Table 9.8, S is the S bit [2] from the MPU Region Attributes and Size Register.

Table 9.9 describes the cache policy for memory attribute encoding.

Cache policy for memory attribute encoding
Memory attribute encoding (AA and BB)Cache policy
01Write back, write and read allocate
10Write through, no write allocate
11Write back, no write allocate


All cache policies presented by HPROT and MEMATTR relate to an outer cache.

Table 9.10 describes the AP encoding.

AP encoding
AP[2:0]Privileged permissionsUser permissionsDescriptions
000No accessNo accessAll accesses generate a permission fault
001Read/writeNo accessPrivileged access only
010Read/writeRead onlyWrites in user mode generate a permission fault
011Read/writeRead/writeFull access
101Read onlyNo accessPrivileged read only
110Read onlyRead onlyPrivileged/user read only
111Read onlyRead onlyPrivileged/user read only

Table 9.11 describes the XN encoding.

XN encoding
0All instruction fetches enabled
1No instruction fetches enabled