For complete descriptions of AXI interface signals, see AMBA AXI Protocol Specification (ARM IHI 0022).
Table A.1 shows the AXI interface signals that have been added or that have different definitions for the Cortex-A8 processor.
Statically selects 64-bit or 128-bit AXI bus width:
0 = 128-bit bus width
1 = 64-bit bus width.
This pin is only sampled during reset of the processor.
AXI clock gate enable:
0 = AXI clock disabled
1 = AXI clock enabled.
The rising edge of the internal ACLK signal comes two CLK cycles after the CLK cycle in which ACLKEN is asserted. See Chapter 10 Clock, Reset, and Power Control.
Read or write cache type:
b0000 = strongly ordered
b0001 = device
b0010 = cacheable, but do not allocate
b0011 = normal noncacheable
b0100 and b0101 are reserved
b0110 = cacheable write-through, allocate on reads only
b0111 = cacheable write-back, allocate on reads only
b1000 and b1001 are reserved
b1010 = cacheable write-through, allocate on writes only
b1011 = cacheable write-back, allocate on writes only
b1100 and b1101 are reserved
b1110 = cacheable write-through, allocate on both reads and writes
b1111 = cacheable write-back, allocate on both reads and writes.