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17.5. L1 and L2 MBIST interfaces

Table 17.5 shows the setup and hold times for the L1 and L2 interfaces

Timing parameters of the L1 and L2 MBIST interface
SignalClockSetup parameterPercent of clock period Hold parameterPercent of clock period
MBISTDATAINL1CLKTismbistdatainl130%Tihmbistdatainl15%
MBISTDSHIFTL1CLKTismbistdshiftl130%Tihmbistdshiftl15%
MBISTMODEL1CLKTismbistmodel130%Tihmbistmodel15%
MBISTRUNL1CLKTismbistrunl130%Tihmbistrunl15%
MBISTSHIFTL1CLKTismbistshiftl130%Tihmbistshiftl15%
MBISTRESULTL1[2:0]CLKTovmbistresultl130%Tihmbistresultl15%
MBISTDATAINL2CLKTismbistdatainl230%Tihmbistdatainl25%
MBISTDSHIFTL2CLKTismbistdshiftl230%Tihmbistdshiftl25%
MBISTMODEL2CLKTismbistmodel230%Tihmbistmodel25%
MBISTRUNL2CLKTismbistrunl230%Tihmbistrunl25%
MBISTSHIFTL2CLKTismbistshiftl230%Tihmbistshiftl25%
MBISTRESULTL2[2:0]CLKTovmbistresultl230%Tohmbistresultl25%
MBISTUSERINL2[18:0]CLKTismbistuserinl230%Tihmbistuserinl25%
MBISTUSEROUTL2[4:0]CLKTovmbistuseroutl250%Tohmbistuseroutl25%
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