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12.9. Cache debug

There are several memory system requirements for a debugger to work optimally on the cached processor:

  • if the debugger performs a memory access while in debug state, caches must not change their state unless the access is a write that hits in the cache

  • if the debugger performs a memory access while in debug state so that the cache state becomes incoherent with memory while in normal state, then one of the following conditions must be true:

    • the memory system detects this situation and performs some implicit operations that keep the cache coherent

    • the processor guarantees that the debugger can restore coherency after the memory access.

  • the means to keep cache coherency must be sufficient so that it does not significantly slow down the debugging process

  • a way to profile cache usage must be available.

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