If bit  of the Debug State Cache Control Register (DSCCR) is set to 0 while the processor is in debug state, then neither the L1 data cache or L2 cache performs any eviction or line fill. However, evictions still occur in any of the following cases:
If identical virtual addresses, except for bit , are mapped to the same physical address and the line that corresponds to the first virtual address is in the L1 data cache, then an access using the second virtual address causes an eviction of the cache line to the L2 cache.
The L1 data cache controller uses a hash algorithm to determine hits. If two different virtual addresses have the same hash and the line that corresponds to the first VA is in the L1 data cache, then an access using the second VA evicts the line to the L2 cache.
No special feature is required to prevent L1 instruction cache pollution because I-side fetches cannot occur while in debug state.