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12.8. Debug state

The debug state enables an external agent, usually a debugger, to control the processor following a debug event. While in debug state, the processor behaves as follows:

  • Sets the DSCR[0] core halted bit.

  • Asserts the DBGACK signal, see DBGACK.

  • Sets the DSCR[5:2] method of entry bits appropriately.

  • Flushes the pipeline and does not prefetch any instructions.

  • Does not change the execution mode and the CPSR.

  • Continues to run the DMA engine. The debugger can stop and restart it using CP15 operations if it has permission.

  • Treats exceptions as described in Exceptions in debug state.

  • Ignores interrupts.

  • Ignores new debug events.

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