The behavior of the PC and CPSR registers while the processor is in debug state is as follows:
The PC is frozen on entry to debug state. That is, it does not increment on the execution of ARM instructions. However, the processor still updates the PC as a response to instructions that explicitly modify the PC.
If the PC is read after the processor has entered debug state, it returns a value as described in Table 12.54, depending on the previous state and the type of debug event.
If the debugger executes a sequence for writing a certain value to the PC and subsequently it forces the processor to restart without any additional write to the PC or CPSR, the execution starts at the address corresponding to the written value.
If the debugger forces the processor to restart without performing a write to the PC, the restart address is Unpredictable.
If the debugger writes to the CPSR, subsequent reads to the PC return an Unpredictable value. If it forces the processor to restart without performing a write to the PC, the restart address is Unpredictable. However, CPSR reads after a CPSR write return the written value.
If the debugger writes to the PC, subsequent reads to the PC return an Unpredictable value.
The processor behavior is Unpredictable when executing a conditional PC-updating instruction while in debug state.
While the processor is in debug state, the CPSR does not change unless an instruction writes to it. In particular, the CPSR IT execution state bits do not change on instruction execution. The CPSR IT execution state bits do not have any effects on instruction execution.
If the processor executes a data processing instruction with Rd == r15 and S == 0, then alu_out must equal the current value of the CPSR T bit. Otherwise, the processor behavior is Unpredictable.