On entry to debug state, the processor does not update any general-purpose or program status register, this includes the SPSR_abt or R14_abt register. Additionally, the processor does not update any coprocessor register, including the CP15 IFSR, DFSR, FAR, or IFAR register, except for CP14 DSCR[5:2] method of debug entry bits. These bits indicate which type of debug event caused the entry into debug state.
On entry to debug state, the processor updates the WFAR register with the virtual address of the instruction accessing the watchpointed address plus:
+ 8 in ARM state
+ 4 in Thumb or ThumbEE state.