When a debug event occurs while the processor is in Halting debug-mode, it switches to a special state called debug state so the debugger can take control. You can configure Halting debug-mode by setting DSCR.
If a halting debug event occurs, the processor enters debug state even when Halting debug-mode is not configured.
While the processor is in debug state, the PC does not increment on instruction execution. If the PC is read at any point after the processor has entered debug state, but before an explicit PC write, it returns a value as described in Table 12.54, depending on the previous state and the type of debug event.
Table 12.54 shows the read PC value after debug state entry for different debug events.
|Debug event||ARM||Thumb and ThumbEE||Return address (RA) meaning|
|Breakpoint||RA+8||RA+4||Breakpointed instruction address|
|Watchpoint||RA+8||RA+4||Address of the instruction that the watchpoint debug event canceled|
|BKPT instruction||RA+8||RA+4||BKPT instruction address|
|Vector catch||RA+8||RA+4||Vector address|
|External debug request signal activation||RA+8||RA+4||Address of the instruction that the external debug request signal activation canceled|
|Debug state entry request command||RA+8||RA+4||Address of the instruction that the debug state entry request command canceled|
|OS unlock catch event||RA+8||RA+4||Address of the instruction that the OS unlock catch event canceled|
|CTI debug request signal activation||RA+8||RA+4||Address of the instruction that the CTI debug request signal activation canceled|
 Watchpoints are imprecise. RA is not the address of the instruction immediately after the one that hit the watchpoint, the processor might stop a number of instructions later. The address of the instruction that hit the watchpoint is in the WFAR.