In debug state, the processor executes instructions issued through the Instruction Transfer Register (ITR). Before the debugger can force the processor to execute any instruction, it must enable this feature through DSCR.
While the processor is in debug state, it always decodes ITR instructions as per the ARM instruction set, regardless of the value of the T and J bits of the CPSR.
The following restrictions apply to instructions executed through the ITR while in debug state:
with the exception of branch instructions and instructions that modify the CPSR, the processor executes any ARM instruction in the same manner as if it was not in debug state
the branch instructions B, BL, BLX(1), and BLX(2) are Unpredictable
certain instructions that normally update the CPSR are Unpredictable
instructions that load a value into the PC from memory are Unpredictable.