The debugger can force the processor to leave debug state by setting the restart request bit, DRCR, to 1. Another way of forcing the processor to leave debug state is through the CTI external restart request mechanism. When one of those restart requests occurs, the processor:
Clears the DSCR core restarted flag.
Leaves debug state.
Clears the DSCR core halted flag.
Drives the DBGACK signal LOW, unless the DSCR DbgAck bit is set to 1.
Starts executing instructions from the address last written to the PC in the processor mode and state indicated by the current value of the CPSR.
Sets the DSCR core restarted flag to 1.