The system can access memory-mapped debug registers through the APB slave port. The system can also access ETM and CTI registers through this port.
The APB slave port is compliant with the AMBA 3 Advanced Peripheral Bus (APB) interface. This APB slave interface supports 32-bits wide data, stalls, slave-generated aborts, and ten address bits [11:2] mapping 4KB of memory. An extra PADDR31 signal indicates to the processor the source of access. See Appendix A Signal Descriptions for a complete list of the debug APB signals.