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SAFESHIFTRAM is a top-level signal with scan enable functionality. It is used to gate off the internal clock of the processor, during shift, to RAMs and register files when MBISTMODE is asserted, as Figure 11.30 shows.

Figure 11.30. SAFESHIFTRAM signal

Figure 11.30. SAFESHIFTRAM signal

One methodology for testing the shadow logic of the RAMs is to test through the RAMs. The ATPG tool uses this gate for easier testability of this logic for this methodology. However, if there is a scan chain or bypass wrapper within the RAM, this gate prevents the clock from toggling during shift and causes the chain or wrapper to be ignored during test. If you do not require this gate, you can optimize it out during synthesis by setting SAFESHIFTRAM LOW.


The SAFESHIFTRAM gate is not selective. Including this gate in a design affects all RAMs and register files when MBISTMODE is asserted.

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