|L1 MBIST Instruction Register||W||See L1 MBIST Instruction Register|
|L2 MBIST Instruction Register||W||See L2 MBIST Instruction Register|
|L1 and L2 MBIST GO-NOGO Instruction Registers||W||See L1 and L2 MBIST GO-NOGO Instruction Registers|
|L1 MBIST Datalog Register||R||See L1 MBIST Datalog Register|
|L2 MBIST Datalog Register||R||See L2 MBIST Datalog Register|
Figure 11.1 shows the fields of the L1 MBIST Instruction Register.
Use the pttn[5:0] field to select test patterns as Table 11.2 shows.
|Field||Selected test pattern|
|pttn[5:0]||Pattern select field:|
6'b010010 = PTTN_WRITE_SOLID
6'b010011 = PTTN_READ_SOLID
6'b100001 = PTTN_SOLIDS
6'b000010 = PTTN_WRITE_CKBD
6'b000011 = PTTN_READ_CKBD
6'b100011 = PTTN_CKBD
6'b000100 = PTTN_XMARCH_C
6'b000101 = PTTN_PTTN_FAIL
6'b000110 = PTTN_RW_XMARCH
6'b000111 = PTTN_RW_YMARCH
6'b001000 = PTTN_RWR_XMARCH
6'b001001 = PTTN_RWR_YMARCH
6'b001010 = PTTN_WRITEBANG
6'b101010 = PTTN_READBANG
6'b001011 = PTTN_YMARCH_C
6'b001100 = PTTN_WRITE_ROWBAR
6'b001101 = PTTN_READ_ROWBAR
6'b101101 = PTTN_ROWBAR
6'b001110 = PTTN_WRITE_COLBAR
6'b001111 = PTTN_READ_COLBAR
6'b101111 = PTTN_COLBAR
6'b010000 = PTTN_RW_XADDRBAR
6'b010001 = PTTN_RW_YADDRBAR
6'b010100 = PTTN_ADDR_DEC
6'b000000 = PTTN_GONOGO
6'b111111 = PTTN_SLAVE
 Default value of pttn[5:0].
The PTTN_SLAVE pattern (6'b111111) is for testing only the I-CAMBIST and D-CAMBIST.
Setting the rtfail bit to 1 enables the fail signal to assert on every cycle that a failure occurs. Clearing the rtfail bit to 0 causes a sticky failure reporting, and the fail signal remains asserted after the first failure that occurs. Reset clears the rtfail bit to 0.
Setting the bitmap bit to1 enables bitmap test mode. Reset clears the instruction register bitmap bit to 0. See Bitmap test mode.
Write the data seed in the dseed field. The MBIST controller repeats the dseed data to the full array bus width. The reset value of dseed[3:0] is 4'b0000.
Set bits in the L1_array_sel[22:0] field to select the L1 arrays for test. The MBIST executes the selected arrays serially beginning with the array indicated by the LSB. Table 11.3 shows how each bit selects one of the L1 arrays. The reset value of the L1_array_sel is 23'h1FFFFF.
|Bit||Array selected||Bit||Array selected|
|||I-RAM word0 [31:0] parity and dirty included.a||||D-RAM word0 [31:0] parity and dirty included.a|
|||I-RAM word1 [63:32] parity and dirty included.a||||D-RAM word1 [63:32] parity and dirty included.a|
|||I-RAM word2 [95:64] parity and dirty included.a||||D-RAM word2 [95:64] parity and dirty included.a|
|||I-RAM word3 [127:96] parity and dirty included.a||||D-RAM word3 [127:96] parity and dirty included.a|
|||I-CAM array.||||D-CAM array.|
|||I-attributes of TLB.||||D-attributes of TLB.|
|||BTBI.||||I-CAMBIST. Tests CAM compare logic.|
|||BTBH.a||||D-CAMBIST. Tests CAM compare logic.|
 You can test the RAM and BTB arrays by accessing the entire array width during writes. The selected words are compared according to the L1_array_sel bit currently under test. For this reason, exercise care when creating iddq or data retention patterns because individual word slices cannot be initialized and maintained with different data seeds.
Do not test the CAMBIST arrays in the same run as other arrays.
The L1_config[14:0] field contains five 3-bit fields for defining the number of physical rows in each L1 array as Table 11.4 shows.
|L1_config bit field||Field name|
The value in each field is implementation-defined and programmable to ensure that physically targeted RAM tests perform correctly.
Only arrays with variable row sizes are programmable. The CAM, PA, and attributes arrays have an architecturally fixed depth of 32. Because of timing limits, physical rows beyond 512 are not supported.
Table 11.5 shows the possible values for each of the 4-bit fields of L1_config[14:0].
|Field value||Number of rows sharing a bitline pair|
Reset clears the HVAB_rows[2:0], GHB_rows[2:0], and TAG_rows[2:0] fields. Reset initializes the BTB_rows[2:0] and DATA_rows[2:0] fields to 3'b010.
Proper physical mapping prevents unintended pattern sequences that result in loss of test quality. This field defines the physical-to-logical address scramble settings for your implementation. Refer to Design for Test implementation documentation for details on how to program this for your design.
Figure 11.2 shows the fields of the L2 MBIST Instruction Register.
The pttn[5:0], rtfail, bitmap, and dseed[3:0] fields function the same as in the L1 MBIST Instruction Register.
Set bits in the L2_ram_sel[4:0] field to select the L2 RAMs for test as Table 11.6 shows.
|||L2 data RAM low order bits [64:0]|
|||L2 data RAM high order bits [129:65]|
|||L2 parity RAM|
|||L2 tag RAM|
|||L2 valid RAM|
Setting an L2_ram_sel bit selects the corresponding RAM for test.
The MBIST accesses the RAMs serially in the order shown in Table 11.6, except that the L2 tag RAM and L2 valid RAM are tested in parallel. You can set the L2ValSer bit to test these two RAMs serially. See L2ValSer.
The reset value of the L2_ram_sel[4:0] field is 5'b11111.
The L2_config[22:0] field contains fields for selecting:
read and write latency of the L2 data array
read and write latency of the L2 tag array
number of rows of the L2 data, parity, tag and valid physical RAM
testing of valid RAM separately or in parallel with tag RAM testing
column address LSB sequencing of 00, 01, 10, 11 or 00, 01, 11, 10.
Table 11.7 shows the bit fields of L2_config[22:0].
Use the L2DLat[3:0] field to select the read and write latency of the L2 data array as Table 11.8 shows. The reset value of the L2DLat[3:0] field is 4'b1111.
Use the L2TLat[1:0] field to select the read and write latency of the L2 tag array as Table 11.9 shows. Reset sets the L2TLat[1:0] field, selecting four wait states.
The four 3-bit fields in the L2Rows[11:0] field control the number of rows in the data, parity, tag, and valid RAMs. Table 11.10 shows the fields that control each of the four RAMs.
|Bit range||Reset value||Function|
|[11:9]||b100||Selects number of data RAM rows|
|[8:6]||b100||Selects number of parity RAM rows|
|[5:3]||b000||Selects number of tag RAM rows|
|[2:0]||b000||Selects number of valid RAM rows|
Table 11.11 shows how to configure array depth with the L2Rows fields.
|Field value||Number of rows sharing a bitline pair|
By default, the MBIST tests the L2 tag RAM and L2 valid RAM at the same time. Table 11.13 shows that you can select serial testing of the tag and valid RAMs by setting the L2ValSer bit. The reset value of the L2ValSer bit is 0.
When L2ValSer is 0, that is, parallel testing is selected, the address scramble configuration for the valid RAM is the same as that of the tag RAM. This means that the valid RAM uses the tag RAM address scramble configuration, even if the tag RAM is not selected for test. The L2ValSer bit is provided to enable you to serially test the tag RAM with different address scramble configurations.
Use the L2AdLSB[3:0] field to select how to increment or decrement the two LSBs of the column address of L2 valid, tag, parity and data RAM accesses. This field is provided as a way to configure non-linear address sequences found in some compiled RAMs. Table 11.14 shows the L2 array controlled by each L2AdLSB[3:0] bit.
|L2AdLSB[3:0] bit||Selected RAM|
|||L2 valid RAM|
|||L2 tag RAM|
|||L2 parity RAM|
|||L2 data RAM|
Table 11.15 shows how each L2AdLSB[3:0] bit controls the increment and decrement sequence of the two column address LSBs.
|L2AdLSB[n]||LSB increment sequence||LSB decrement sequence|
|||00, 01, 10, 11||11, 10, 01, 00|
|||00, 01, 11, 10||10, 11, 01, 00|
The reset value of the L2AdLSB[3:0] field is 4'b0000.
Proper physical mapping prevents unintended pattern sequences that result in loss of test quality. Use the ADDR_SCRAMBLE[289:0] field to define the physical-to-logical address scramble setting for your implementation. Refer to Design for Test implementation documentation for details on how to program this for your design.
You can use the L1 and L2 MBIST GO-NOGO Instruction Registers to program a custom sequence of up to eight patterns for either L1 or L2 memory. Figure 11.3 shows the fields of the L1 and L2 MBIST GO-NOGO Instruction Registers.
GO-NOGO describes the default GO-NOGO sequence available at power-up.
Each GNG[10:0] field is a concatenation of three fields as Table 11.16 shows.
|GNG[10:0] bit field||Field name|
The patterns execute in order, starting with GNG1. It is not necessary to load the entire register when fewer than eight patterns are required. If you load fewer than eight patterns, the unloaded fields cannot execute because their valid bits are cleared at reset.
For example, to execute a READBANG with a data seed of
by a COLBAR with a data seed of
0xF, you only
have to load two fields:
1_0110_101010 → 1_1111_10111 = GNG1[10:0] → GNG2[10:0]
Figure 11.4 shows
the L1 MBIST GO-NOGO Instruction Register contents after loading
a COLBAR with a data seed of
0xF and a READBANG
with a data seed of
The MBISTSHIFTL1 signal must toggle one cycle before initiation and one cycle before completion of the MBISTDATAINL1 stream as Figure 11.7 shows. During GO-NOGO instruction load, MBISTDSHIFTL1 must toggle at the same time as MBISTSHIFTL1. See Figure 11.8.
The L1 MBIST Datalog Register records information about failing arrays. Figure 11.5 shows the fields of the L1 MBIST Datalog Register.
Read the ArrayFail[22:0] field to identify arrays that produce failures. The bits in this field correspond to the bits in the L1_array_sel[22:0] field in the L1 MBIST Instruction Register. Table 11.3 shows how each bit corresponds to one of the L1 arrays. Testing more than one array while not in bitmap test mode can set more than one ArrayFail[22:0] bit. The least-significant 1 in the ArrayFail[22:0] field indicates the first failing array.
Read the expect_data[3:0] field for the expected data seed for the first failing array. Because data seed toggling occurs throughout pattern execution, the value in this field does not always correspond to the programmed data seed.
Read the fail_addr[16:2] field for the physical address of the first failing array. See the address scramble information contained within the Design for Test implementation documentation for details on shows how this address is constructed.
Read the failing_bits[37:0] field to identify failing bits in the first array that fails. This field contains the EXCLUSIVE-OR of read data and expect data.
For the first failing array, read the alg_pass[3:0] field to identify which pass of the algorithm produced a failure. For example, the CKBD algorithm has four passes, wscan, rscan, wscan, and rscan, numbered 1, 2, 3, and 4. Because failures only occur on reads, a CKBD failure results in an alg_pass[3:0] value of 4'b0010 or 4'b0100.
Read the pattern[5:0] field to identify the pattern running at the time of the first failure. Table 11.2 shows the pattern codes. This field is useful when running more than one pattern during a GO-NOGO test.
Figure 11.6 shows the fields of the L2 MBIST Datalog Register.
Read the failing_ram[4:0] field to identify the RAMs that produce failures. The bits in this field correspond to the bits in the L2_ram_sel[4:0] field in the L2 MBIST Instruction Register. Table 11.6 shows how each bit corresponds to one of the L2 RAMs. Testing more than one RAM while not in bitmap test mode can set more than one failing_ram[4:0] bit. The least-significant bit that is set to 1 in the failing_ram[4:0] field indicates the first failing RAM.
When the L2ValSer bit is 0, the tag RAM and valid RAM are tested in parallel. When testing both these RAM in parallel, a failure in either RAM sets both bit  and bit  in the failing_ram[4:0] field. To determine if the tag RAM, valid RAM, or both failed, process the failing_bits[32:0] field, see Table 11.18.
Read the expect_data[3:0] field for the expected data seed for the first failing RAM. Because data seed toggling occurs throughout algorithm execution, the value in this field does not always correspond to the programmed data seed.
Read the fail_addr[16:0] field for the physical address of the first RAM failure. This is the address sent to the RAM through the L2 MBIST interface. See the address scramble information contained within the Design for Test implementation documentation for details on how you can construct this address.
When testing the data array, there are no cache way select bits, but the index value is still right-justified with fail_addr. You can ignore the values shifted out of unused address bits. Those values reflect the values assigned to those bits in the address scramble configuration.
When testing the tag array, bits [16:15] of this field contain the cache way select bits, and the tag array index value is the least-significant bits of fail_addr. Because the fail_addr[14:12] bits are not used for the tag array, they are always zero.
Table 11.17 shows how the cache ways are grouped into two ways of read data sent back from the tag RAMs.
|Test sequence number||Cache way grouping in read data|
|0||way 1, way 0|
|1||way 3, way 2|
|2||way 5, way 4|
|3||way 7, way 6|
 Test sequence number is the order that the MBIST controller accesses the cache ways.
The lower-numbered cache ways are always assigned to bits [22:0] of the read data bus for the current test group. The valid RAM contains two data bits for each of the eight cache ways for a total of 16 bits. To achieve a high test quality, all 16 bits are tested in parallel when testing the first group of cache ways. Because the valid bits are typically implemented as a single 16-bit RAM, testing all cache ways in parallel enables the full 16 bits to be accessed each time instead of testing it in slices. This provides greater flexibility with data backgrounds and can reduce test time if the valid RAM is tested serially after the tag RAM.
When testing tag RAMs and valid RAMs in parallel, the valid RAM chip select is disabled to prevent the valid RAM from being accessed during testing of subsequent groups of cache ways within the tag array.
The read_mux bit indicates which half of the 65-bit read produced the first failure:
Indicates failure in bits [31:0].
Indicates failure in bits [64:32].
Read the failing_bits[32:0] field to identify failing bits in the first RAM that fails. This field contains the EXCLUSIVE-OR of read data and expect data. Table 11.18 shows how to identify failing L2 bits.
|Data, low order||0||1'b0, data RAM bits [31:0]|
|Data, low order||1||Data RAM bits [64:32]|
|Data, high order||0||1'b0, data RAM bits [96:65]|
|Data, high order||1||Data RAM bits [129:97]|
|Parity||0||17'b0, parity RAM bits [15:0]|
|Tag/valid RAMs||0||1'b0, tag RAM read bits [15:0], valid RAM read bits [15:0]|
|Tag/valid RAMs||1||3'b0, tag RAM read bits [45:16]b|
 The read_mux value for the parity RAM is always 0 because it is only 16 bit-wide and is always stored in the lower half of the 65-bit read bus.
 For L2 cache sizes greater than 64K, not all tag RAM read bits are active. The MBIST controller masks any unused bits and does not generate a failure.
Read the alg_pass[3:0] field to identify which pass of the algorithm produced a failure in the first failing RAM. A pass is defined as one complete pass through the entire address space of the RAM under test. The numbering starts with 4'b0001, indicating the first pass.
Read the pattern[5:0] field to identify the pattern running at the time of the first failure. Table 11.2 shows the pattern codes. This field is useful in GO-NOGO testing when more than one pattern is run during the test.