The ID Register, at offset
0x1E4, is a
32-bit read-only register that provides information about the ETM
architecture version and options supported. Figure 14.2 shows the bit arrangement
of the ID Register.
Table 14.3 shows how the bit values correspond with the ID Register functions.
Indicates implementor, ARM:
Reserved, Read As Zero (RAZ) on reads.
Indicates TrustZone support. The processor supports TrustZone architectural extensions. If this bit is not set, then the ETM behaves as if the processor is in secure state at all times.
All 32-bit Thumb instructions are traced as a single instruction, including BL and BLX immediate.
Reserved, RAZ on reads.
Load pc first
All data transfers are traced in the same order that they appear in the ARM Architecture Reference Manual.
ARM core family
Indicates the Cortex-A8 processor.
Major ETM architecture version
Indicates the major ETM architecture version number, ETMv3.
Minor ETM architecture version
Indicates the minor ETM architecture version number, ETMv3.3.
Indicates the implementation revision.