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1.1. About the processor

The Cortex-A8 processor is a high-performance, low-power, cached application processor that provides full virtual memory capabilities. The features of the processor include:

  • full implementation of the ARM architecture v7-A instruction set

  • configurable 64-bit or 128-bit high-speed Advanced Microprocessor Bus Architecture (AMBA) with Advanced Extensible Interface (AXI) for main memory interface supporting up to 22 outstanding transactions

  • a pipeline for executing ARM integer instructions

  • a NEON pipeline for executing NEON and VFP instruction sets

  • dynamic branch prediction with branch target address cache, global history buffer, and 8-entry return stack

  • Memory Management Unit (MMU) and separate instruction and data Translation Look-aside Buffers (TLBs) of 32 entries each

  • Level 1 instruction and data caches of 16KB or 32KB configurable size

  • Level 2 cache of 0KB, 64KB through 2MB configurable size

  • Level 2 cache with parity and Error Correction Code (ECC) configuration option

  • Level 2 cache configuration option that supports one, two, or four tag banks

  • Embedded Trace Macrocell (ETM) support for non-intrusive debug

  • ARMv7 debug with watchpoint and breakpoint registers and a 32-bit Advanced Peripheral Bus (APB) interface to the CoreSight debug system.

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