This manual is for revision r1p1 of the Cortex-A8 processor. See Product revision status for details of revision numbering. The following changes have been made in this release:
Corrections for r1p0 errata
Change to ID Register values to reflect r1p1 revision
The L2EN bit of the Auxiliary Control Register is banked between Nonsecure and Secure states
SAFESHIFTRAM top-level pin addition for ATPG test.
Support for ETM and NEON configurability.