The L2 cache is 8-way set associative of configurable size. The cache is physically addressed. The cache sizes are configurable with sizes in the range of 0KB, 64KB, 128KB, 256KB, 512KB, 1MB, and 2MB.
You can reduce the effective cache size using lockdown format C. This feature enables you to lock cache ways to prevent allocation to locked entries.
You can configure the L2 memory pipeline to insert wait states to take into account the latencies of the compiled memories for the implemented RAMs.
To enable streaming of NEON read accesses from the L1 data cache, the L2 memory system supports up to eight NEON read accesses. The write buffer handles integer write, NEON writes, and eviction accesses from the L1 data cache. This enables streaming of write requests from the L1 data cache.
The L2 cache incorporates a dirty bit per quadword to reduce AXI traffic. This eliminates unnecessary transfer of clean data on the AXI interface.