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13.6.2. IEEE 754 standard implementation choices

Some of the implementation choices permitted by the IEEE 754 standard and used in the VFPv3 architecture are described in the ARM Architecture Reference Manual.

NaN handling

Any single-precision or double-precision values with the maximum exponent field value and a nonzero fraction field are valid NaNs. A most significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. Table 13.13 shows the default NaN values in both single and double precision.

Default NaN values
Fractionbit [22] = 1 bits [21:0] are all zerosbit [51] = 1 bits [50:0] are all zeros

Any SNaN passed as input to an operation causes an Invalid Operation exception and sets the IOC flag, FPSCR[0]. A default QNaN is written to the destination register. The rules for cases involving multiple NaN operands are in the ARM Architecture Reference Manual.

Processing of input NaNs for ARM floating-point coprocessors and libraries is defined as follows:

  • In full-compliance mode, NaNs are handled according to the ARM Architecture Reference Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data transfer operations, NaNs are transferred without raising the Invalid Operation exception. For the non-arithmetic CDP instructions, FABS, FNEG, and FCPY, NaNs are copied, with a change of sign if specified in the instructions, without causing the Invalid Operation exception.

  • In default NaN mode, NaNs are handled completely within the hardware. SNaNs in an arithmetic CDP operation set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions is the same as in full-compliance mode. Arithmetic CDP instructions involving NaN operands return the default NaN regardless of the fractions of any NaN operands.

Table 13.14 summarizes the effects of NaN operands on instruction execution.

QNaN and SNaN handling
Instruction typeDefault NaN modeWith QNaN operandWith SNaN operand
Arithmetic CDPOffThe QNaN or one of the QNaN operands, if there is more than one, is returned according to the rules given in the ARM Architecture Reference Manual.IOC[1] set. The SNaN is quieted and the result NaN is determined by the rules given in the ARM Architecture Reference Manual.
OnDefault NaN returns.IOCb set. Default NaN returns.
Non-arithmetic CDPOffNaN passes to destination with sign changed as appropriate.
FCMP(Z)-Unordered compare.IOC set. Unordered compare.
FCMPE(Z)-IOC set. Unordered compare.IOC set. Unordered compare.
Load/storeOffAll NaNs transferred.

[1] IOC is the Invalid Operation exception flag, FPSCR[0].


Comparison results modify condition code flags in the FPSCR Register. The FMSTAT instruction transfers the current condition code flags in the FPSCR Register to the CPSR Register. See the ARM Architecture Reference Manual for mapping of IEEE 754 standard predicates to ARM conditions. The condition code flags used are chosen so that subsequent conditional execution of ARM instructions can test the predicates defined in the IEEE 754 standard.

The VFPLite coprocessor handles all comparisons of numeric and reserved values in hardware, generating the appropriate condition code depending on whether the result is less than, equal to, or greater than.

The VFPLite coprocessor supports:

Compare operations

The compare operations are FCMPS, FCMPZS, FCMPD, and FCMPZD.

A compare instruction involving a QNaN produces an unordered result. An SNaN produces an unordered result and generates an Invalid Operation exception.

Compare with exception operations

The compare with exception operations are FCMPES, FCMPEZS, FCMPED, and FCMPEZD.

A compare with exception operation involving either an SNaN or a QNaN produces an unordered result and generates an Invalid Operation exception.


In the generation of Underflow exceptions, the before rounding form of tininess and the inexact result form of loss of accuracy as described in the IEEE 754 standard, are used.

In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE 754 standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual for information on flush-to-zero mode.

When the VFPLite coprocessor is not in flush-to-zero mode, operations are performed on subnormal operands. If the operation does not produce a tiny result, it returns the computed result, and the UFC flag, FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set.


The VFPLite coprocessor implements the VFPv3 architecture and sets all exception status bits in the FPSCR register as required for each instruction. The VFPLite coprocessor does not support user-mode traps. The VFPLite coprocessor ignores exception enable bits in the FPSCR register.

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