You copied the Doc URL to your clipboard.

2.2. Thumb-2 architecture

Thumb-2 is an enhancement to the 16-bit Thumb Instruction Set Architecture (ISA). It adds 32-bit instructions that can be freely intermixed with 16-bit instructions in a program. The additional 32-bit instructions enable Thumb-2 to cover the functionality of the ARM instruction set. The 32-bit instructions enable Thumb-2 to deliver the code density of earlier versions of Thumb, together with performance of the existing ARM instruction set, all within a single instruction set.

The most important difference between the Thumb instruction set and the ARM instruction set is that most 32-bit Thumb instructions are unconditional, whereas most ARM instructions can be conditional. Thumb-2 introduces a conditional execution instruction, IT, that is a logical if-then-else function that you can apply to following instructions to make them conditional.

Thumb-2 instructions are accessible as were Thumb instructions when the processor is in Thumb state, that is, the T bit in the CPSR is 1 and the J bit in the CPSR is 0.

In addition to the 32-bit Thumb instructions, there are several 16-bit Thumb instructions and a few 32-bit ARM instructions, introduced as part of the Thumb-2 architecture.

The main enhancements are:

  • 32-bit instructions added to the Thumb instruction set to:

    • provide support for exception handling in Thumb state

    • provide access to coprocessors

    • include Digital Signal Processing (DSP) and media instructions

    • improve performance in cases where a single 16-bit instruction restricts functions available to the compiler.

  • addition of a 16-bit IT instruction that enables one to four following Thumb instructions, the IT block, to be conditional

  • addition of a 16-bit Compare with Zero and Branch (CZB) instruction to improve code density by replacing two-instruction sequence with a single instruction.

The 32-bit ARM Thumb-2 instructions are added in the space occupied by the Thumb BL and BLX instructions. Figure 2.1 shows the 32-bit ARM Thumb-2 instruction format.

Figure 2.1. 32-bit ARM Thumb-2 instruction format

Figure 2.1. 32-bit ARM Thumb-2 instruction format

The first halfword (hw1) determines the instruction length and functionality. If the processor decodes the instruction as 32-bit long, then the processor fetches the second halfword (hw2) of the instruction from the instruction address plus two.

The availability of both 16-bit Thumb and 32-bit instructions in the Thumb-2 instruction sets, gives you the flexibility to emphasize performance or code size on a subroutine level, according to the requirements of their applications. For example, you can code critical loops for applications such as fast interrupts and DSP algorithms using the 32-bit media instructions in Thumb-2 and use the smaller 16-bit classic Thumb instructions for the rest of the application. This is for code density and does not require any mode change.

See the ARM Architecture Reference Manual, Thumb-2 supplement for details on the Thumb-2 instruction set architecture. For details of the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual.

Was this page helpful? Yes No