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2.7. VFPv3 architecture

The VFP architecture v3 is an enhancement to the VFP architecture v2. The main changes are:

  • the doubling of the number of double-precision registers to 32

  • the introduction of an instruction that places a floating-point constant in a register, and instructions that perform conversions between fixed-point and floating-point numbers

  • the introduction of VFP architecture v3U, that does not trap floating-point exceptions.

VFPv3 is backward compatible with VFPv2 except for the capability of trapping floating-point exceptions.

See the ARM Architecture Reference Manual, Advanced SIMD Extension and VFPv3 supplement for details of VFPv3.

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