A precise watchpoint exception has similar behavior as a precise data abort exception with the following differences:
If the processor is in Halting debug-mode R14_abt and SPSR_abt are not updated.
If the processor is in Monitor debug-mode the DFSR is updated with the encoding for a debug event, DFSR[10,3:0] = b00010. If the processor is in Halting debug-mode the DFSR is unchanged.
If the processor is in Monitor debug-mode the DFAR is Unpredictable.
The DSCR[5:2] bits are set to Precise Watchpoint Occurred.
If the watchpointed access is subject to a precise data abort, then the precise abort takes priority over the watchpoint because it is a higher priority exception. If the watchpointed access is subject to an imprecise data abort, then the watchpoint takes priority.