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12.7.1. Effect of debug exceptions on CP15 registers and WFAR

The four CP15 registers that record abort information are:

  • Data Fault Address Register (DFAR)

  • Instruction Fault Address Register (IFAR)

  • Instruction Fault Status Register (IFSR)

  • Data Fault Status Register (DFSR).

See Chapter 3 System Control Coprocessor for more information on these registers.

If the processor takes a debug exception because of a watchpoint debug event, the processor performs the following actions on these registers:

  • it does not change the IFSR or IFAR

  • it updates the DFSR with the debug event encoding

  • it writes an Unpredictable value to the DFAR

  • it updates the WFAR with the address of the instruction that accessed the watchpointed address, plus a processor state dependent offset:

    • + 8 for ARM state

    • + 4 for Thumb and ThumbEE states.

If the processor takes a debug exception because of a breakpoint, BKPT, or vector catch debug event, the processor performs the following actions on these registers:

  • it updates the IFSR with the debug event encoding

  • it writes an Unpredictable value to the IFAR

  • it does not change the DFSR, DFAR, or WFAR.

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