There are two MBIST modes:
Manufacturing test mode determines the pass or fail status of the arrays. If the failure flag is set to 1 when the complete flag is set to 1, you can retrieve the datalog to identify the failing arrays. After analyzing the datalog, you can use bitmap test mode to identify the failing bits.
In manufacturing test mode, an MBIST test consists of the following steps:
Assert MBISTMODE for the entire test.
MBIST pipeline flush. Assert the system reset signal for at least 15 cycles.
Instruction load. Write to the MBIST Instruction Register.
Test execute. Wait for complete flag or fail flag.
Datalog retrieval. If the fail pin, MBISTRESULT, is HIGH, read the MBIST Datalog Register.
In bitmap test mode, the MBIST controller stops when it detects a failure. It asserts MBISTRESULT until the tester begins datalog retrieval. After datalog retrieval, the MBIST controller resumes the test from the point where it stopped. This handshake continues until test completion. The collected datalogs are useful for offline bitmap and redundancy analysis.
In bitmap test mode, an MBIST test consists of the following steps:
Figure 11.7 shows the timing of an MBIST instruction load. The MBISTMODE signal must remain asserted while the core is under reset. See Figure 10.6 for more information on reset timing. MBISTSHIFT is asserted and instruction load data is serially loaded into the Instruction Register through the MBISTDATAIN pin. MBISTSHIFT is deasserted upon completion of the instruction load. MBISTDATAIN has one cycle of latency in relation to MBISTSHIFT.
Figure 11.8 shows an example of an MBIST instruction load followed immediately by a GO-NOGO instruction load. During the GO-NOGO portion of the load, MBISTDSHIFT and MBISTSHIFT both equal 1.
Figure 11.9 shows an example of normal MBIST test execution. The complete flag, MBISTRESULT, is asserted at the end of the test. This indicates a pass result in the absence of MBISTRESULT, the fail flag. While bitmap mode is enabled, the test execution is interrupted when a failure occurs to shift out the fail data. Figure 11.9 shows the timing wave forms for at speed test of the core. Slow clocking is implemented during the shifting of the Instruction Register and fast clocking is for the actual MBIST execution. It is assumed that slow clocking is required because of packaging pin timing restrictions.
During at-speed clocking with real-time fail mode active, you can ignore MBISTRESULT.
Figure 11.10 shows an example of retrieval of the first failure datalog and the pass/fail status for every array. This is typically run at the end of testing. You can use bitmap test mode on the failing arrays.
Be careful not to miss a subsequent failure that might occur near the end of the testing sequence. For example, if a failure occurs on the last RAM access of the test sequence, then the complete flag asserts only three at-speed cycles after the fail flag asserts. If the fail flag signal goes through more external delay than the complete flag, the complete flag might be visible externally before the fail flag. Before classifying a test as passing, give adequate time after recognizing the complete flag to ensure that the fail flag does not assert.
Figure 11.11 shows an example of the start of a failure datalog retrieval during bitmap mode. The fail flag remains asserted and no further MBIST testing occurs until the MBISTDSHIFT signal is asserted, which initiates the serial shift-out of the bitmap datalog. This provides time to switch from fast to slow clocking required for shifting.
Figure 11.12 shows an example of the end of a failure datalog retrieval during the execution of a failure bitmap. When all of the bits are shifted out, the PLL switches back to fast clocking and negates the MBISTDSHIFT signal. This causes the MBIST controller to resume testing.