The L2 cache is enabled when both the C bit of the CP15 Control Register c1 and the L2EN bit of the CP15 Auxiliary Control Register, c1, are both active. If either of these bits is disabled, then the L2 cache is disabled.
To enable the L2 cache following a reset or to change the settings of the L2 Cache Auxiliary Control Register, you must use the following sequence:
Complete the processor reset sequence or disable the L2 cache.
Program the L2 Cache Auxiliary Control Register. See c9, L2 Cache Auxiliary Control Register for details.
If you have configured the processor to support parity or ECC memory, you must enable those features before you can program the C bit.
Program the Auxiliary Control Register to set the L2EN bit to 1. See c1, Auxiliary Control Register for details.
Program the C bit in the CP15 Control Register c1. See c1, Control Register for details.
To disable the L2 cache, but leave the L1 data cache enabled, use the following sequence:
Disable the C bit.
Clean and invalidate the L1 and L2 caches.
Disable the L2 cache by clearing the L2EN bit to 0.
Enable the C bit.
To keep memory coherent when using cache maintenance operations, you must follow the L2 cache disabling sequence. Cache maintenance operations have an effect on the L1 and L2 caches when they are disabled. A cache maintenance operation can evict a cache line from the L1 data cache. If the L2EN bit is set to 1, the evicted cache line can be allocated to the L2 cache. If the L2EN bit is not set to 1, then evictions from the L1 data cache are sent directly to external memory using the AXI interface.