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16.2. Instruction-specific scheduling for ARM instructions

The tables in this section provide information to determine the best-case instruction scheduling for a sequence of instructions. The information includes:

  • when source registers are required

  • when destination registers are available

  • which register, such as Rn or Rm, is meant for each source or destination

  • the minimum number of cycles required for each instruction

  • any additional instruction issue requirements or restrictions.

When a source register is required or a destination register is available depends on the availability of forwarding paths to route the required data from the correct source to the correct destination.

Special considerations and caveats concerning the instruction tables include:

  • Source requirements are always given for the first cycle in a multi-cycle instruction.

  • Destination available is always given with respect to the last cycle in a data processing multi-cycle instruction. This rule does not apply to load/store multiple instructions.

  • Multiply instructions issue to pipeline 0 only.

  • Flags from the CPSR Register are updated internally in the E2 stage.

  • [Rd] as a source register indicates the destination register is required as a source if the instruction is conditional.

  • {} on a source register indicate the register is required only if the instruction includes an accumulator operand.

  • () on a destination register indicate the destination is required only if writeback is enabled.

  • [] on a load instruction destination register indicate that the destination register is optional depending on the size of the data transferred.

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