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16.8. Scheduling example

Example 16.6 shows a sample code segment and how the processor might schedule it.

Cycle  PC          Opcode     Instruction              Timing description
  1    0x00000ed0: 0xe12fff1e BX r14                   Dual issue pipeline 0
  1    0x00000ee4: 0xe3500000 CMP r0,#0                Dual issue in pipeline 1
  2    0x00000ee8: 0xe3a03003 MOV r3,#3                Dual issue pipeline 0
  2    0x00000eec: 0xe3a00000 MOV r0,#0                Dual issue in pipeline 1
  3    0x00000ef0: 0x05813000 STREQ r3,[r1,#0]         Dual issue in pipeline 0, r3 not needed until E3
  3    0x00000ef4: 0xe3520004 CMP r2,#4                Dual issue in pipeline 1
  4    0x00000ef8: 0x979ff102 LDRLS pc,[pc,r2,LSL #2]  Single issue pipeline 0, +1 cycle for load to
                                pc, no extra cycle for shift since LSL #2
  5    0x00000f2c: 0xe3a00001 MOV r0,#1                Dual issue with 2nd iteration of load in
                                pipeline 1
  6    0x00000f30: 0xea000000 B {pc}+8                 #0xf38 dual issue pipeline 0
  6    0x00000f38: 0xe5810000 STR r0,[r1,#0]           Dual issue pipeline 1
  7    0x00000f3c: 0xe49df004 LDR pc,[r13],#4          Single issue pipeline 0, +1 cycle for load to pc
  8    0x0000017c: 0xe284200c ADD r2,r4,#0xc           Dual issue with 2nd iteration of load in
                                pipeline 1
  9    0x00000180: 0xe5960004 LDR r0,[r6,#4]           Dual issue pipeline 0
  9    0x00000184: 0xe3a0100a MOV r1,#0xa              Dual issue pipeline 1
 12    0x00000188: 0xe5900000 LDR r0,[r0,#0]           Single issue pipeline 0: r0 produced in E3,
                                                       required in E1, so +2 cycle stall
 13    0x0000018c: 0xe5840000 STR r0,[r4,#0]           Single issue pipeline 0 due to LS resource
                                hazard, no extra delay for r0 since produced in
                                                       E3 and consumed in E3
 14    0x00000190: 0xe594000c LDR r0,[r4,#0xc]         Single issue pipeline 0 due to LS resource
                                hazard
 15    0x00000194: 0xe8bd4070 LDMFD r13!,{r4-r6,r14}   Load multiple loads r4 in 1st cycle, r5 and r6                                                        in 2nd cycle, r14 in 3rd cycle, 3 cycles total
 17    0x00000198: 0xea000368 B {pc}+0xda8             #0xf40 dual issue in pipeline 1 with 3rd cycle
                                                       of LDM
 18    0x00000f40: 0xe2800002 ADD r0,r0,#2 ARM         Single issue in pipeline 0
 19    0x00000f44: 0xe0810000 ADD r0,r1,r0 ARM         Single issue in pipeline 0, no dual issue due to
                                                       hazard on r0 produced in E2 and required in E2
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