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1.8. Product revisions

This manual is for revision r2p1 of the Cortex-A8 processor. See Product revision status for details of revision numbering. This section summarizes the differences in functionality between the releases of this processor.

Note

The first released version of the Cortex-A8 processor was r1p0.

r1p0 - r1p1

The following changes have been made in this release:

  • Maintenance upgrade to fix errata.

  • ID Register values changed to reflect r1p1 revision.

  • The L2EN bit of the Auxiliary Control Register is banked between Nonsecure and Secure states.

  • SAFESHIFTRAM top-level pin added for ATPG test.

  • ETM and NEON configurability support added.

r1p1 - r2p0

The following changes have been made in this release:

  • Maintenance upgrade to fix errata.

  • ID Register values changed to reflect r2p0 revision.

  • CLKSTOPREQ and CLKSTOPACK functionality added to stop and restart the processor clocks without relying on software to execute WFI instruction.

  • The SAFESHIFTRAM signal is replaced with the SAFESHIFTRAMIF, SAFESHIFTRAMLS, and SAFESHIFTRAML2 signals for ATPG test.

  • Intelligent Energy Management (IEM) multiple power domain support added.

  • 1-way and 4-way L2 tag bank removed.

  • 64KB and 2MB L2 cache sizes removed.

  • ETMPWRDWNREQ and ETMPWRDWNACK are no longer required because debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0. See Static or leakage power management for information on the supported Cortex-A8 power domain configurations.

r2p0 - r2p1

The following changes have been made in this release:

  • Maintenance upgrade to fix errata.

  • ID Register values changed to reflect r2p1 revision.

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