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7.5.2. Data cache behavior with C-bit disabled

The C bit in CP15 Control Register c1 enables or disables the L1 data cache. See c1, Control Register for more information on caching data when enabling the data cache. If the C bit is disabled, then memory requests do not access any of the data cache arrays.

An exception to this rule is the CP15 data cache operations. If the data cache is disabled, all data cache maintenance operations can still execute normally.