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7.5.1. Data cache preload instruction

ARMv7-A specifies the PLD instruction as a preload hint instruction. The processor uses the PLD instruction to preload cache lines to the L2 cache. If the PLD instruction results in a L1 cache hit, L2 cache hit, or TLB miss no further action is taken. If a cache miss and TLB hit result, the line is retrieved from external memory and is loaded into the L2 memory cache.