An instruction can remain in the pipeline between being fetched and being executed. Because there can be several unresolved branches in the pipeline, instruction fetches are speculative, meaning there is no guarantee that they are executed. A branch or exceptional instruction in the code stream can cause a pipeline flush, discarding the currently fetched instructions.
Fetches or instruction table walks that begin without an empty pipeline are marked speculative. If the pipeline contains any instruction up to the point of branch and exception resolution, then the pipeline is considered not empty. If a fetch is marked speculative and misses the L1 instruction cache and the L2 cache, it is not forwarded to the external interface. Fetching is suspended until all outstanding instructions are resolved or the pipeline is flushed.
This behavior is controlled by the ASA bit in the CP15 Auxiliary Control Register c1. See c1, Auxiliary Control Register for information on the ASA bit. By default, this bit is 0, indicating that speculative fetches or instruction table walks are not forwarded to the external interface. If this bit is set to 1, then neither fetches nor instruction table walks are marked speculative, and are forwarded to the external interface.
Given the aggressive prefetching behavior, you must not place read-sensitive devices in the same page as code. Pages containing read-sensitive devices must be marked with the TLB XN (execute never) attribute bit.