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8.2.2. L2 cache transfer policy

Table 8.1 describes instruction and data transfers to and from the L2 cache.

L2 cache transfer policy
Request typeL2 hitL2 miss
Instruction miss (read)L2 −> L1

AXI −> L1

AXI −> L2

Data miss (read)L2 −> L1

AXI −> L1

AXI −> L2

NEON (read)L2 −> NEON

AXI −> NEON

AXI −> L2

Data or NEON (write)

Write data −> L2

Read, modify, and write to recalculate error correction code if necessary

Initiates write allocate fill

AXI (merged with write data) −> L2

TLB table walk (instruction or data)L2 −> TLB

AXI −> TLB

AXI −> L2