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8.4. L2 PLE

The L2 cache controller supports transactions from a programmable preloading engine. This PLE is not the same Dynamic Memory Allocation (DMA) engine used in previous ARM family of processors but has a similar programming interface.

The L2 PLE has two channels to permit two blocks of data movement to or from the L2 cache RAM.

The L2 PLE shares the translation table base TTBR0, TTBR1 and control, TTBCR, registers with the main translation table walk hardware.

The L2 PLE also supports the ability to lock data to a specific L2 cache way. If software requires the data to always remain resident in the L2 cache way, software can lock the specific cache way per channel when the PLE transfers data to or from the L2 cache RAM. Locking of a specified way only guarantees that the PLE is within the L2 cache RAM after completion. If the way is not locked, it is possible that the software might have evicted or replaced data with the way that the PLE is transferring data. To lock a cache way, you must program the L2 Cache Lockdown Register c9. See c9, L2 Cache Lockdown Register for more information.

The programming of other registers within the PLE is possible only within the secure privileged state with specific extensions as described in this section. You can reprogram this capability using the Nonsecure Access Control Register and setting the PLE bit [18] to 1. If you program any register in nonsecure privileged state when the PLE bit [18] is 0, an Undefined Instruction exception occurs. Additionally, you can use the software to program the L2 Preload Engine Control Register UM bit [26] to 1 to enable more accessibility to the PLE registers.