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6.1. About the MMU

The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls accesses to and from external memory. See the ARM Architecture Reference Manual for a full architectural description of the MMU.

The processor implements the ARMv7-A MMU enhanced with Security Extensions features to provide address translation and access permission checks. The MMU controls table walk hardware that accesses translation tables in main memory. The MMU enables fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in instruction and data TLBs.

The MMU features include the following:

  • full support for Virtual Memory System Architecture version 7 (VMSAv7)

  • separate, fully-associative, 32-entry data and instruction TLBs

  • support for 32 lockable entries using the lock-by-entry model

  • TLB entries that support 4KB, 64KB, 1MB, and 16MB pages

  • 16 domains

  • global and application-specific identifiers to prevent context switch TLB flushes

  • extended permissions check capability

  • round-robin replacement policy

  • CP15 TLB preloading instructions to enable locking of TLB entries.