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3.2.36. c5, Instruction Fault Status Register

The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last instruction fault.

The Instruction Fault Status Register is:

  • a read/write register banked for Secure and Nonsecure states

  • accessible in privileged modes only.

Figure 3.31 shows the bit arrangement of the Instruction Fault Status Register.

Figure 3.31. Instruction Fault Status Register format

Figure 3.31. Instruction Fault Status Register

Table 3.69 shows how the bit values correspond with the Instruction Fault Status Register functions.

Instruction Fault Status Register bit functions
[31:13]-Reserved. UNP, SBZ.

Indicates whether an AXI Decode or Slave error caused an abort. This bit is only valid for external aborts. For all other aborts this bit Should-Be-Zero:

0 = AXI Decode error caused the abort, reset value

1 = AXI Slave error caused the abort.

[11]-Reserved. UNP, SBZ.

Part of the Status field. See bits [3:0] in this table.

[9:4]-Reserved. UNP, SBZ.

Indicates the type of exception generated. To determine the data fault, bits [12] and [10] must be used in conjunction with bits [3:0]. The following encodings are listed in priority order, highest first:

  • bx01100 L1 translation, precise external abort

  • bx01110 L2 translation, precise external abort

  • b011100 L1 translation precise parity error

  • b011110 L2 translation precise parity error

  • b000101 translation fault, section

  • b000111 translation fault, page

  • b000011 access flag fault, section

  • b000110 access flag fault, page

  • b001001 domain fault, section

  • b001011 domain fault, page

  • b001101 permission fault, section

  • b001111 permission fault, page

  • bx01000 precise external abort, nontranslation

  • b011001 precise parity error

  • b000010 debug event.

Any unused encoding not listed is reserved.

Where x represents bit [12] in the encoding, bit [12] can be either:

0 = AXI Decode error caused the abort, reset value

1 = AXI Slave error caused the abort.


When the SCR EA bit is set to 1, see c1, Secure Configuration Register, the processor writes to the Secure Instruction Fault Status Register on a Monitor entry caused by an external abort.

To access the Instruction Fault Status Register, read or write CP15 with:

MRC p15, 0, <Rd>, c5, c0, 1 ; Read Instruction Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 1 ; Write Instruction Fault Status Register