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12.12.6. Scenarios and usage models

This section describes the different debugging scenarios for systems with energy management capabilities along with a description of how the debug features help with those.

Application debug on a stable OS

For this system, set the DBGNOPWRDWN signal to 1 to emulate power down.

Application debug on an OS with save and restore capability

For this system, application debug is possible without power-down emulation if the OS supports storing and recovering of the debug registers. This is useful in systems where either:

  • the save and restore capability is already implemented in the OS

  • power-down emulation is undesirable because it makes it difficult to reproduce the error

  • the system design does not support the power-down emulation.


The debugger or debug monitor can program the debug logic to trigger a debug event on clearing of the OS lock.

Debugging of the power-up sequence

When debugging the OS power-up sequence:

  • The processor can be identified while the core is powered down.

  • The internal signal ARESETn can be held on power up. If bit [2] of the PRCR is set to 1, the nondebug logic of the processor is held in reset on power up. When this bit is set to 1, it enables the debugger to wait for the power-up event to occur, reprogram the debug registers, and start execution by clearing this bit to 0.

  • The EDBGRQ or DRCR[0] halting debug events can be set to 1 at any point in time, even if the core is powered down.

  • The debugger can set PRCR[2] to 1, wait for the power-up event to occur, assert EDBGRQ or DRCR[0], and clear the PRCR[2] bit to 0 for the processor to enter debug state on executing the first instruction. This enables single-stepping of the power-up sequence.

When the debugger detects a slave-generated error response, it indicates that one of the following is true:

  • the debug registers are not available because the core is powered down

  • the debug registers are not available because the OS locks the APB interface

  • the debug registers are available but the error response warns that a previous power-down event cleared them, that is, the sticky power down bit is set to 1.