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7.3.3. Normal

Normal memory type can have the following attributes:

  • noncacheable, bufferable

  • write-back cached, write-allocate

  • write-through cached, no allocate on write, buffered

  • write-back cached, no allocate on write, buffered.

Table 7.1 shows how L1 and L2 memory systems handle these memory types.

Memory types affecting L1 and L2 cache flows
L1 inner policy[1]L2 outer policyBuffers flushedDescription

Strongly ordered

Strongly ordered

Yes

Noncacheable and nonbufferable.
Device sharedDevice sharedNoDevice accesses are noncacheable and must be executed nonspeculative.
Device nonsharedDevice nonsharedNoDevice accesses are noncacheable and must be executed nonspeculative.
Noncacheable, nonbufferableCacheable, write-back, no write-allocateNoLoads and stores are not cached at L1. Loads are not filled into the fill buffer but are allocated to the L2 cache. Stores bypass integer store buffer and are directly sent to L2.
Noncacheable, nonbufferableCacheable, write-back, write-allocateNoLoads and stores are not cached at L1. Loads are not filled into the fill buffer but are allocated to the L2 cache. Stores bypass integer store buffer and are directly sent to L2. L2 store misses allocate the line into L2 cache.
Noncacheable, nonbufferable Cacheable, write-through, no write-allocateNoLoads and stores are not cached at L1. Loads are not filled into the fill buffer. Stores bypass integer store buffer and are directly sent to L2. L2 store misses do not allocate the line into L2 cache. Store hits are sent externally in addition to updating L2.
Cacheable, write-back, no write-allocateNoncacheable, nonbufferableNoLoad misses are filled into L1. Store misses are sent to L2. L2 does not allocate the line into L2 cache on an L2 miss but is sent externally.
Cacheable, write-back, write-allocateNoncacheable, nonbufferableNoThis is not supported. L1 is always in the no write-allocate mode.
Cacheable, write-through, no write-allocateNoncacheable, nonbufferableNoLoad misses are filled into L1. Store hits and store misses are sent to L2. L2 does not allocate the line into L2 cache on an L2 miss because it is sent externally.
Cacheable, write-back, no write-allocateCacheable, write-back, no write-allocateNoLoad misses are allocated into L1. Store misses bypass integer store buffer and are sent to L2. Store hits update the cache. L2 does not allocate the line into L2 cache on store misses.
Cacheable, write-back, no write-allocateCacheable, write-back, write-allocateNoLoad misses are allocated into L1. Store misses bypass integer store buffer and are sent to L2. Store hits update the cache. L2 allocates the line into L2 cache for store misses.
Cacheable, write-back, no write-allocateCacheable, write-through, no write-allocateNoLoad misses are allocated into L1. L2 makes store hits write-through at L2 cache and does not allocate the line into L2 for store misses.
Cacheable, write-through, no write-allocateCacheable, write-back, no write-allocateNoLoads are allocated into L1. Store hits are made write-through at L1. Store hits update the cache and are sent to L2. L2 does not allocate store misses but they are sent externally.
Cacheable, write-through, no write-allocateCacheable, write-back, write-allocateNoLoads are allocated into L1. Store hits are made write-through at L1. Store hits update the cache and are sent to L2. Store misses are allocated into L2.
Cacheable, write-through, no write-allocateCacheable, write-through, no write-allocateNoLoads are allocated into L1. Store hits are made write-through at L1. Store hits update the cache and are sent to L2. Store misses are not allocated into L2.
Noncacheable, bufferableNoncacheable, bufferableNoLoads are replayed and access is sent externally. Stores bypass integer store buffer and are placed into L2 write buffer. Stores are sent externally.

[1] You can configure the L2 cache to use the inner policy attributes.

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