The processor has three separate MBIST controllers:
- L1 and L2 MBIST controllers
The L1 and L2 MBIST controllers communicate with RAM arrays distributed around the chip. Their controls are directly ported to the interface for use with external testbench or Automated Test Equipment (ATE) drivers.
- CAMBIST controller
The CAMBIST controller is a slave of the L1 MBIST controller. It targets the comparator logic of the Content-Addressable Memory (CAM). The L1 MBIST controller tests the contents of the I-CAM and D-CAM arrays.
The following arrays require MBIST support:
Instruction cache (I-cache)
Data cache (D-cache)
Global History Buffer (GHB)
Branch Target Buffer (BTB)
Translation Look-aside Buffer (TLB)
The TLB has separate instruction and data arrays, each containing an attribute array, a CAM array, and a Physical Address (PA) array.
Hash Virtual Address Buffer (HVAB)
L1 tag RAM
all L2 cache RAM such as data, parity, tag, and valid RAMs.