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7.1. About the L1 memory system

The L1 memory system consists of separate instruction and data caches in a Harvard arrangement. The L1 memory system provides the core with:

  • fixed line length of 64 bytes

  • support for 16KB or 32KB caches

  • two 32-entry fully associative ARMv7-A MMU

  • data array with parity for error detection

  • virtually indexed, physically tagged caches

  • 4-way set associative cache structure

  • random replacement policy

  • nonblocking cache behavior for Advanced SIMD code

  • blocking for integer code

  • MBIST

  • support for hardware reset of the L1 data cache valid RAM, see Hardware RAM array reset.

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