The purpose of cache parity error detection is to increase the tolerance to memory faults.
The instruction cache RAM is written on cache linefills. Parity error detection is done on a fetch-wide basis, that is, a parity error on any byte in a 64-bit fetch region causes a parity error on the first instruction within that fetch. The detection of a parity error instruction cache RAM causes the processor to return a Prefetch Abort.
When the processor executes the instruction:
the address of the fetch containing the parity error is stored in the Instruction Fault Address Register
the Instruction Fault Status Register is set to indicate the presence of a parity error.