The AXI protocol specifies that, when a locked transaction
occurs, the master must follow the locked transaction with an unlocked
transaction to remove the lock of the interconnect. The locked sequence
is not complete until the end of the locking transaction. The SWP{B,H}
instructions
include separate read and write transactions on the AXI. The read
transaction is marked as a locked transaction while the write transaction
is not marked as a locked transaction. Therefore, the write transaction
serves as the unlocking transaction and the AXI interconnect is
unlocked when the write response is generated.
The SWP{B,H}
instructions can access cacheable
or noncacheable memory. If it is to cacheable memory, the bus transaction
is not marked as a locked transaction. If it is to noncacheable
memory, both the read and write transactions are treated as strongly ordered
memory type, and the bus transaction is marked as a locked transaction.
If an abort occurs, the swapping of data between the register and memory is unsuccessful. To clear the lock, the processor issues a write transaction on the AXI interface without any byte strobes active.
Note
All transactions related to the swap instructions are issued with the lock indicator on its respective port, ARLOCK or AWLOCK.