When the processor generates a memory access, the MMU:
Performs a hardware translation table walk if the lookup in step 1 misses.
The MMU might not find global mapping, mapping for the currently selected ASID, or a matching NSTID for the virtual address in the TLB. The hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the TTB Control Register. If translation table walks are disabled, the processor returns a Section Translation fault.
If the MMU finds a matching TLB entry, it uses the information in the entry as follows:
The access permission bits and the domain determine if the access is enabled. If the matching entry does not pass the permission checks, the MMU signals a memory abort. See the ARM Architecture Reference Manual for a description of abort types and priorities, and for a description of the Instruction Fault Status Register (IFSR) and Data Fault Status Register (DFSR).
The memory region attributes specified in the CP15 c10 registers control the cache and write buffer, and determine if the access is secure or nonsecure, cached or noncached, and device or shared.
The MMU translates the virtual address to a physical address for the memory access.
If the MMU does not find a matching entry, a hardware table walk occurs.