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2.17.3. Secure monitor bus

The SECMONOUT bus exports a set of signals from the processor.

You must ensure that the SECMONOUT signals do not compromise the security of the processor.

The SECMONOUTEN input enables the security monitor output SECMONOUT[86:0]. The SECMONOUTEN signal is sampled at reset. Any change to the state of this pin during functional operation is ignored.

See Appendix A Signal Descriptions for a list of signals that appear on the secure monitor bus SECMONOUT[86:0].

SECMONOUT protocol

The following pseudo code shows the protocol of SECMONOUT[86:0].

if SECMONOUTEN = 0 at reset, then

        SECMONOUT[86:0] holds its value

else if SECMONOUTEN = 1 at reset, then

        if SECMONOUT[86] = 1, then
            valid L1 data address present on SECMONOUT[59:40]
        else 
            invalid L1 data address

        if SECMONOUT[85] = 1, then
            valid exception data present on SECMONOUT[64:60]
        else 
            invalid exception data

        if SECMONOUT[82] = 1, then
            valid pipeline 1 instruction address on SECMONOUT[39:20]
            valid pipeline 1 condition code fail on SECMONOUT[84]
        else 
            invalid instruction or condition code in pipeline 1

        if SECMONOUT[81] = 1, then
            valid pipeline 0 instruction address on SECMONOUT[19:0]
            valid pipeline 0 condition code fail on SECMONOUT[83]
        else 
            invalid instruction or condition code in pipeline 0

        any change of state is exported for the following pins:
            SECMONOUT[80]    DMB or DWB executed
            SECMONOUT[79]    IMB executed
            SECMONOUT[78]    instruction caches at all levels enabled if set
                              to 1 or disabled if cleared to 0