The purpose of the system control and configuration registers is to provide overall management of:
Security Extensions behavior
program flow prediction
coprocessor access rights for CP0-CP13.
The system control and configuration registers also provide the processor ID. Some of the functionality depends on how you set external signals at reset.
System control and configuration behaves in three ways:
as a set of flags or enables for specific functionality
as a set of numbers, values that indicate system functionality
as a set of addresses for processes in memory.
The processor supports a primary input pin, CP15SDISABLE, to disable write access to the CP15 registers.
When the CP15SDISABLE input is set to 1, any attempt to write to the secure version of the banked register, NS-bit is 0, or any non-banked register, NS-state is 0 results in an Undefined Instruction exception.
Changes in the pin on an instruction boundary occur as quickly
as practically possible after a change to this pin. Software must
IMB after a change to this pin has occurred
on the boundary of the macros to ensure that its effects are recognized
on following instructions.
At reset, it is expected that this pin is set to logic 0 by the SoC hardware. Control of this pin is expected to remain within the SoC chip that implements the processor.
Table 3.2 shows the CP15 registers affected by the primary input pin, CP15SDISABLE.
Translation Table Base 0
Translation Table Control Register
Domain Access Control
Primary Region Remap
Normal Memory Region Remap