The purpose of Debug Feature Register 0 is to provide information about the debug system for the processor.
The Debug Feature Register 0 is:
a read-only register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.6 shows the bit arrangement of the Debug Feature Register 0.
Table 3.16 shows how the bit values correspond with the Debug Feature Register 0 functions.
Microcontroller debug model – memory-mapped
Indicates support for the microcontroller debug model:
Trace debug model – memory-mapped
Indicates support for the trace debug model – memory-mapped:
Trace debug model – coprocessor-based
Indicates support for the coprocessor-based trace debug model:
Core debug model – memory mapped
Indicates support for the memory-mapped debug model:
Secure debug model – coprocessor-based
Indicates support for the secure debug model – coprocessor:
Core debug model – coprocessor-based
Indicates support for the coprocessor debug model:
Table 3.17 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Debug Feature Register 0, read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 2 ; Read Debug Feature Register 0