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3.2.19. c0, Instruction Set Attributes Register 4

The purpose of Instruction Set Attributes Register 4 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 4 is:

  • a read-only register common to the Secure and Nonsecure states

  • accessible in privileged modes only.

Figure 3.15 shows the bit arrangement of the Instruction Set Attributes Register 4.

Figure 3.15. Instruction Set Attributes Register 4 format

Figure 3.15. Instruction Set Attributes Register
4 format

Table 3.35 shows how the bit values correspond with the Instruction Set Attributes Register 4 functions.

Table 3.35. Instruction Set Attributes Register 4 bit functions
BitsFieldFunction
[31:24]-

Reserved, RAZ.

[23:20]

Exclusive

instructions

Indicates support for exclusive instructions:

0x0 = The processor supports CLREX, LDREX{B|H}, and STREX{B|H}.

[19:16]

Barrier

instructions

Indicates support for barrier instructions:

0x1 = The processor supports DMB, DSB, and ISB.

[15:12]

SMC

instructions

Indicates support for SMC instructions:

0x1 = The processor supports SMC.

[11:8]

Write-back

instructions

Indicates support for write-back instructions:

0x1 = The processor supports all defined write-back addressing modes.

[7:4]

With-shift

instructions

Indicates support for with-shift instructions.

0x4 = The processor supports:

  • shifts of loads and stores over the range LSL 0-3

  • constant shift options

  • register-controlled shift options.

[3:0]

Unprivileged

instructions

Indicates support for Unprivileged instructions:

0x2 = The processor supports LDR{SB|B|SH|H}T.


Table 3.36 shows the results of attempted access for each mode.

Table 3.36. Results of access to Instruction Set Attributes Register 4[18]
Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[18] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Instruction Set Attributes Register 4, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 4 ; Read Instruction Set Attributes Register 4