The purpose of the Memory Model Feature Register 0 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 0 is:
a read-only register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.7 shows the bit arrangement of the Memory Model Feature Register 0.
Table 3.19 shows how the bit values correspond with the Memory Model Feature Register 0 functions.
Indicates support for fast context switch memory mappings:
Auxiliary Control Register
Indicates support for Auxiliary Control Register:
Indicates support for TCM and associated DMA:
Indicates support for outer shareable attribute:
Indicates support for cache coherency maintenance:
Indicates support for Physical Memory System Architecture (PMSA):
Indicates support for Virtual Memory System Architecture (VMSA).
Table 3.20 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Memory Model Feature Register 0, read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 4 ; Read Memory Model Feature Register 0