The purpose of Processor Feature Register 0 is to provide information about the execution state support and programmer’s model for the processor.
The Processor Feature Register 0 is:
a read-only register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.4 shows the bit arrangement of the Processor Feature Register 0.
Table 3.12 shows how the bit values correspond with the Processor Feature Register 0 functions.
Indicates support for Thumb Execution Environment (ThumbEE):
Indicates support for Jazelle extension interface:
Indicates the type of Thumb encoding that the processor supports:
Indicates support for ARM instruction set:
Table 3.13 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Processor Feature Register 0, read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 0 ; Read Processor Feature Register 0