The purpose of the Control Register is to provide control and configuration of:
memory alignment, endianness, protection, and fault behavior
MMU, cache enables, and cache replacement strategy
interrupts and behavior of interrupt latency
location for exception vectors
program flow prediction.
The Control Register is:
a 32-bit read/write register
accessible in privileged modes only
Figure 3.20 shows the bit arrangement of the Control Register.
Table 3.46 shows how the bit values correspond with the Control Register functions.
Reserved. UNP, SBZP.
Thumb exception enable bit:
0 = Enables ARM exception generation. On exception entry, the CPSR T bit is 0 and J bit is 0.
1 = Enables Thumb exception generation. On exception entry, the CPSR T bit is 1 and J bit is 0.
The primary input CFGTE defines the reset value.
This is the Access Flag Enable bit. It controls whether VMSAv7 redefines the AP bit as an access flag or whether the software maintains binary compatibility with VMSAv6:
0 = AP behavior defined, reset value
1 = access flag behavior defined.
The TLB must be invalidated after changing the AFE bit.
This bit controls the TEX remap functionality in the MMU, see MMU software-accessible registers:
0 = TEX remap disabled. Normal ARMv6 or later behavior, reset value.
1 = TEX remap enabled. TEX[2:1] become translation table bits for OS.
This is the Non-Maskable Fast Interrupt enable bit. The reset value is determined by CFGNMFI. The pin cannot be configured by software:
0 = FIQ exceptions can be masked by software
1 = FIQ exceptions cannot be masked by software.
Reserved. RAZ, SBZP.
Determines how the E bit in the CPSR is set on an exception:
0 = CPSR E bit is set to 0 on an exception
1 = CPSR E bit is set to 1 on an exception.
The primary input CFGEND0 defines the reset value of the EE bit.
This field returns 11'b01100010100 when read.
Determines the location of exception vectors, see c12, Secure or Nonsecure Vector Base Address Register. The primary input VINITHI defines the reset value of the V bit:
0 = Normal exception vectors selected, reset value. The Vector Base Address Registers determine the address range.
1 = High exception vectors selected,
address range =
Determines if instructions can be cached in any instruction cache at any cache level:0 = instruction caching disabled at all levels, reset value
1 = instruction caching enabled.
Enables program flow prediction:
0 = program flow prediction disabled, reset value
1 = program flow prediction enabled.
Reserved. RAZ, SBZP.
Reserved. Read-As-One (RAO), Should-Be-One or Preserved (SBOP).
Determines if data can be cached in a data or unified cache at any cache level:0 = data caching disabled at all levels, reset value
1 = data caching enabled.
Enables strict alignment of data to detect alignment faults in data accesses:
0 = strict alignment fault checking disabled, reset value
1 = strict alignment fault checking enabled.
Enables the MMU:
0 = MMU disabled, reset value
1 = MMU enabled.
Attempts to read or write the Control Register from secure or nonsecure User modes result in an Undefined Instruction exception.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Security Extensions write access disable.
Table 3.47 shows the actions that result from attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
|Secure bit||Secure bit||Nonsecure bit||Nonsecure bit||Undefined||Undefined||Undefined||Undefined|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Control Register, read or write CP15 with:
MRC p15, 0, <Rd>, c1, c0, 0 ; Read Control Register
MCR p15, 0, <Rd>, c1, c0, 0 ; Write Control Register
|I bit||C bit||L2EN bit||Description|
|0||0||-||Instruction cache, data cache, L2 cache disabled for all instruction and data requests|
|0||1||0||Instruction cache disabled, data cache enabled, L2 cache disabled for all instruction and data requests|
|0||1||1||Instruction cache disabled, data cache enabled, L2 cache enabled for all instruction and data requests|
|1||0||-||Instruction cache enabled, data cache disabled, L2 cache disabled for all instruction and data requests|
|1||1||0||Instruction cache enabled, data cache enabled, L2 cache disabled for all instruction and data requests|
|1||1||1||Instruction cache, data cache, and L2 cache enabled for all requests|